More Information
- Workplace Type On-site (Employees come to work in-person)
- Job Locality Whitefield
- Minimum Experience 3 Years
Job Requirements
We are seeking a highly skilled Memory Layout Engineer with hands-on expertise in designing and implementing layouts for advanced memory components. The ideal candidate will have strong experience in memory circuit layout, process technology nodes, and deep understanding of design-for-manufacturability in cutting-edge technologies.
Key Responsibilities
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Design and optimize layouts for critical memory components, including:
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Control and Digital Logic
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Sense Amplifiers
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Bit-cell Arrays
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Decoders
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Collaborate with circuit design engineers to ensure accurate schematics-to-layout translation.
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Perform layout verification including DRC, LVS, and parasitic extraction.
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Optimize for performance, area, power, and yield while ensuring manufacturability.
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Work closely with technology teams to align design with process rules and best practices.
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Contribute to memory compiler/layout automation methodologies.
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Debug and resolve issues related to layout, parasitics, and process variations.
Process Technology Expertise
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Proven hands-on experience with advanced nodes: 16nm, 14nm, 10nm, 7nm, 5nm, and 3nm.
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Strong expertise in FinFET and other advanced device architectures.
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Familiarity with EDA tools such as Cadence Virtuoso, Mentor Calibre, Synopsys ICC, or equivalent.
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Understanding of design challenges at sub-10nm technology nodes.
Qualifications & Requirements
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Bachelor’s or Master’s degree in Electronics, Electrical Engineering, VLSI Design, or related field.
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3–7 years of experience in custom layout design, specifically memory/analog/mixed-signal domains.
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Strong analytical and problem-solving skills with attention to detail.
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Ability to work independently as well as within cross-functional teams.
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Good communication and documentation skills.
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