RTL Design 54 views1 application

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Job Requirements

  1. Work experience in designing IP’s ,Subsystems involving CPU/high speed bus interconnects
  2. RTL design experience using Verilog/System Verilog, scripting language (Perl,Python, shell, TCL)
  3. Working experience in UCIe/CXL/PCIe and AXI/AHB is a plus
  4. Exposure to high speed data path arch/design upwards of 500 Mhz clock frequency
  5. prior experience in leading a team( for 10+ yrs candidates)

 

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