More Information
- Workplace Type On-site (Employees come to work in-person)
- Work Location India
- Minimum Experience 8 Years
Job Requirements
- Work experience in designing IP’s ,Subsystems involving CPU/high speed bus interconnects
- RTL design experience using Verilog/System Verilog, scripting language (Perl,Python, shell, TCL)
- Working experience in UCIe/CXL/PCIe and AXI/AHB is a plus
- Exposure to high speed data path arch/design upwards of 500 Mhz clock frequency
- prior experience in leading a team( for 10+ yrs candidates)
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