Synthesis Engineer 25 views1 application

Job Summary:

We are seeking a highly motivated and experienced Synthesis Engineer to join our growing team in Chennai. The ideal candidate will have 3-5 years of experience in RTL synthesis, timing closure, and related areas. You will be responsible for implementing and optimizing synthesis flows for complex digital designs, ensuring high performance, low power, and area efficiency. You will collaborate closely with RTL designers, physical design engineers, and verification engineers to deliver successful tape-outs.

Responsibilities:

• RTL Synthesis: Perform RTL synthesis using industry-standard tools (e.g., Synopsys Design Compiler, Cadence Genus) to generate optimized gate-level netlists.
• Timing Closure: Analyze and resolve timing violations (setup, hold, clock skew) using static timing analysis (STA) tools (e.g., PrimeTime, Tempus).
• Constraint Development: Develop and maintain synthesis constraints (SDC) to meet performance, power, and area targets.
• Power Optimization: Implement power optimization techniques during synthesis, including clock gating, multi-voltage design, and power gating.
• Area Optimization: Optimize gate-level netlists for area efficiency while meeting performance and power requirements.
• Design for Test (DFT): Collaborate with DFT engineers to ensure proper insertion of scan chains and other DFT structures during synthesis.
• Scripting and Automation: Develop and maintain scripts (Tcl, Perl, Python) to automate synthesis flows and improve efficiency.
• Flow Development: Contribute to the development and improvement of synthesis methodologies and flows.
• Collaboration: Work closely with RTL designers, physical design engineers, and verification engineers to resolve design issues and ensure successful tape-outs.
• Documentation: Maintain clear and concise documentation of synthesis flows, constraints, and results.
• Tool Evaluation: Evaluate and recommend new synthesis tools and methodologies.
• Debug: Debug synthesis and timing related issues.