Design Verification 108 views51 applications

Should have experience and/or knowledge in the following areas:
·     Verification of architecture and low-level hardware functionality
·     Hands-on experience with System Verilog and/or UVM verification methodology. Create verification environments using System Verilog and Universal verification methodology-UVM for networking chips
·     Excellent knowledge of programming languages like C/C++, Integrate C model into systemverilog verification Environments
·     Good working knowledge of various scripting languages like Python/TCL/Perl
·     Familiar with Hardware description languages (Verilog/SystemVerilog/SystemC), high-level languages (C/C++), and scripting languages (Perl, Tcl)
·     Debugging complicated problems or bugs